1. Field of the Invention
The present invention relates to a capacitor of a memory device and, more particularly, to a method of forming a bottom electrode of a capacitor in a memory device.
2. Description of the Related Art
Recently, semiconductor materials have been popularly employed to form memory devices and logic devices to provide various electronic consumer products, such as televisions, refrigerators, personal computers, video games, digital cameras, cellular phones, portable computers, image-sound facilities, and personal digital assistants (PDAs). A Metal-Oxide-Semiconductor (MOS) transistor, the most important device in numerous semiconductor products, basically comprises a gate electrode, a drain region and a source region, in which a channel effect between the source region and drain region is formed at different gate voltages to determine the on/off states of the MOS transistor. Thus, the MOS transistor, serving as a digital and solid-state switch, is integrated into IC devices with other functional devices. A typical dynamic random access memory (DRAM) device has a memory cell array and peripheral circuits, such as sensing amplifiers. Each memory cell comprises a MOS field effect transistor and a capacitor formed on a silicon semiconductor substrate, in which the source region of the transistor is electrically connected to the charge-storage electrode of the capacitor. There is much interest in reducing the size of the DRAM device in order to increase its density on an integrated circuit (IC) chip, and thereby reduce size of the transistor or the capacitor. For the capacitor process, since stacked-type capacitors occupy a larger area and encounter increased capacitance with the increased height, as limited by semiconductor processes, a deep trench capacitor has been developed to provide higher capacitance within a lower profile. This is made possible by the more easily controlled depth of the deep trench in the substrate. However, as the depth of the deep trench increases, the difficulty in forming the bottom electrode of the capacitor is likewise increased.
FIGS. 1A to 1G are sectional diagrams showing a conventional deep trench capacitor process. As shown in FIG. 1A, an active area 110 and a peripheral area 120 are defined on a semiconductor substrate 100, and then an oxide layer 102 and a silicon nitride layer 104 are successively deposited on the semiconductor substrate 100 to serve as a pad layer 107. Preferably, the oxide layer 102 of 50xcx9c100 xc3x85 thickness is formed by oxidation, and the silicon nitride layer 104 of 1600xcx9c3000 xc3x85 thickness is formed by chemical vapor deposition (CVD). Next, using the CVD method, a shielding layer 108 of boron-doped boron silicon glass (BSG) and 5000xcx9c20000 xc3x85 thickness is deposited on the pad layer 107.
As shown in FIG. 1B, using photolithography and etching to move parts of the shielding layer 108, the pad layer 107 and the semiconductor substrate 100, a plurality of first deep trenches 112 is formed within the active area 110, and a plurality of second deep trenches 114 is formed within the peripheral area 120. Preferably, the number of the second deep trench 114 is lower than that of the first deep trench 112, that is, the arranged density of the second deep trenches 114 within the peripheral area 120 is lower than that of the first deep trenches 112 within the active area 110. Then, the shielding layer 108 is etched to expose the pad layer 107. Next, using low pressure chemical vapor deposition (LPCVD) with a diffusion process, an ion implantation, or an in-situ implantation, a arsenic-doped oxide layer 116 of approximately 300 xc3x85 thickness is formed on the exposed surface of the pad layer 107 and the sidewall/bottom of the first/second deep trenches 112 and 114.
As shown in FIG. 1C, a photoresist layer is coated on the doped oxide layer 116 to fill the deep trenches 112 and 114, in which a photoresist layer 130 fills the first deep trenches 112 and a photoresist layer 140 fills the second deep trenches 114. Since the arranged density of the second deep trenches 114 within the peripheral area 120 is lower than that of the first deep trenches 112 within the active area 110, the photoresist layer 140 within the peripheral area 120 is thicker than the photoresist layer 130 within the active area 110. The difference in thickness between the photoresist layer 130 and the photoresist layer 140, indicated by the symbol xe2x80x9caxe2x80x9d, is approximately 3000xc3x85.
As shown in FIG. 1D, using etching to remove a part of the photoresist layer, the photoresist layer remaining in the first deep trench 112 is indicated as a photoresist layer 130xe2x80x2, and the photoresist layer remaining in the second deep trench 114 is indicated as a photoresist layer 140xe2x80x2. Since the photoresist layer 140 within the peripheral area 120 is thicker than the photoresist layer 130 within the active area 110, the photoresist layer 140xe2x80x2 is thicker than the photoresist layer 130xe2x80x2. The difference in thickness between the photoresist layer 130xe2x80x2 and the photoresist layer 140xe2x80x2, that is the step height, indicated by the symbol xe2x80x9cbxe2x80x9d, is approximately 6000xc3x85.
As shown in FIG. 1E, continuously using isotropic etching to remove the exposed portion of the doped oxide layer 116 higher than the photoresist layers 130xe2x80x2 and 140xe2x80x2, a part of the semiconductor substrate 100 on the sidewall of the first/second deep trenches 112 and 114 is exposed. Hereinafter, the remaining portions of doped oxide layer 116 within the first deep trench 112 and the second deep trench 114 are indicated as a doped oxide layer 142 and a doped oxide layer 144, respectively. The difference in thickness between the doped oxide layer 142 and the doped oxide layer 144, that is the step height, indicated by the symbol xe2x80x9cbxe2x80x9d, is approximately 6000xc3x85.
As shown in FIG. 1F, the photoresist layer 130xe2x80x2 within the first deep trenches 112 and the photoresist layer 140xe2x80x2 within the second deep trenches 114 are completely removed.
As shown in FIG. 1G, an oxide layer (not shown) is formed by LPCVD to cover the entire exposed surface of the semiconductor substrate 100, and then the dopants in the doped oxide layers 142 and 144 are driven into the semiconductor substrate 100 by a drive-in process. Thus, the diffusion regions 150 and 155 surrounding the doped oxide layers 142 and 144, respectively, serve as bottom electrodes of the capacitor. Finally, the oxide layer, the doped oxide layers 142 and 144, and the pad layer 107 are removed to complete the bottom electrode process.
However, since the different arranged densities of deep trenches in the active area 110 and the peripheral area 120 cause differences in the step height between doped oxide layer 142 within the active area 110 and the doped oxide layer 144 within the peripheral area 120, the bottom electrode 150 within the active area 110 and the bottom electrode 155 within the peripheral area 120, different capacitances occur in the active area 110 and the peripheral area 120. This may affect the original setting functions to inhibit the functionality of the memory device incapable of normal work.
The present invention provides a method of forming a bottom electrode of a deep trench capacitor in a DRAM process, which controls the incident angle of the light source on the photoresist layer during the exposure process to equalize the heights of the bottom electrodes within the active area and the peripheral area.
In the method of forming a bottom electrode of a capacitor in a memory device, an active area and a peripheral area are defined on a semiconductor substrate, and then a pad layer and a shielding layer are successively formed on the semiconductor substrate. Next, parts of the shielding layer, the pad layer and the semiconductor substrate are removed to form a plurality of first deep trenches within the active area and a plurality of second deep trenches within the peripheral area, wherein the number of the first deep trenches is higher than the number of the second deep trenches. Next, a doped oxide layer is formed on the entire surface of the semiconductor substrate to cover the surfaces of the pad layer, the sidewall and bottom of the first deep trenches and the second deep trenches. Thereafter, a photoresist layer is formed on the doped oxide layer to fill the first deep trenches and the second deep trenches. Then, exposure is employed on the photoresist layer with a predetermined incident angle of light source, wherein the photoresist layer outside the level of the deep trenches is exposed, but the photoresist layer inside the deep trenches is not. Thus, the photoresist layer exposed and outside the level of the deep trenches is removed, and the photoresist layer that is not exposed and inside the deep trenches is retained. Next, a part of the photoresist layer inside the first deep trenches and the second deep trenches is removed. Next, the doped oxide layer outside the level of the photoresist layer is removed to expose the semiconductor substrate on parts of the sidewalls of the first deep trenches and the second deep trenches. Thereafter, the photoresist layer remaining in the first deep trenches and the second deep trenches is removed. Then, an oxide layer is formed on the entire surface of the semiconductor substrate. Next, a drive-in process diffuses the dopants of the doped oxide layer into the exposed semiconductor substrate to form a bottom electrode surrounding the doped oxide layer. Finally, the oxide layer, the doped oxide layer and the pad layer are removed.
Accordingly, it is a principal object of the invention to equalize the heights of the bottom electrodes of the deep trench capacitor within the active area and within the peripheral area.
It is another object of the invention to equalize the capacitance of the deep trench capacitors within the active area and within the peripheral area.